|||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| supervisory circuit 2015 - 0 9 - 000 2 pt01 97 - 4 0 9 / 1 5 / 1 5 1 pt7m 6315us features ? highly accurate: ? 1.5% (25c) ? detect voltage range: 1.8 to 5v in 100mv increments ? operating voltage range: 1.0v ~ 5.5v ? operating temperature range: - 40c to + 85c ? detect voltage temperature characteristics: ? 2.5% ? typ ? output configuration: n - cha nnel open drain ? three r eset timeout period available: ? typical 1.6 ms for pt7m6315usxx d 1 ; ? typical 26ms for pt7m6315usxxd2 ; ? typical 200ms for pt7m6315usxxd 3; ? typical 1570ms for pt7m6315usxxd4 ; description the seri e s are designed to monitor power supplies in p and digital systems. it provides excellent circuit reliability and low cost by eliminating exte rnal components and adjustments, and a debounced manual reset input. this device performs a single function: it asserts a reset signal whenever the v cc sup ply voltage falls below a preset threshold or whenever manual reset is asserted. reset remains asserted for an internally programmed interval (reset timeout period) after v cc has risen above the reset threshold or manual reset is deasserted. the pt7m 6315u sxx are open - drain reset output. they can be pulled up to a voltage higher than v cc . the serials come with factory - trimmed reset threshold voltages in 100mv increments from 1.8v to 5v. preset timeout periods of 200ms (typ.) for pt7m6315usxxd 3, 1570ms (typ .) for pt7m6315usxxd4 , and 26ms for pt7m6315usxxd2 are available. pin configuration pin description name type description rst i/o reset output: rst is asserted when v cc drops below voltage threshold v th - . active low. mr i manu al reset: a logic low on mr asserts reset. reset remains asserted as long as mr is low, and for the reset timeout period (t rs ) after the reset conditions are terminated. connect to v cc if not used. gnd p ground v cc p supply voltage. 1 2 v cc rst gnd 3 4 mr pt7m6315usxxd3f/d4f sot143-4
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||| 2015 - 0 9 - 000 2 pt01 97 - 4 0 9 / 1 5 / 1 5 2 pt7m6315us supervisory circuit block diagram function description power monitor a microprocessors (ps) reset input starts the p in a known state. whenever the p is in an unknown state, it should be held in reset. the supervisory circuits assert reset during pow er - up and prevent code execution errors during power - down or brownout conditions. on power - up, once vcc reaches about 1 . 0 v, rst is a guaranteed logic low of 0.4v or less. as vcc rises, rst stays low. when vcc rises above the reset threshold v rst , an internal timer releases rst after about 200ms (pt7m 6315usxxd3 ) or 1570ms (pt7m 6315usxx d4) or 26ms ( pt7m 6315usxx d 2 ) or 1.6ms (pt7m6315usxxd1) . rst asserts whenever vcc drops below the reset threshold, i.e. brownout condition. if brownout occurs in the midd le of a previously initiated reset pulse, the pulse continues for at least another 200ms (pt7m 6315usxxd3 ) or 1570ms (pt7m 6315usxx d4) or 26ms ( pt7m 6315usxx d 2 ) or 1.6ms (pt7m6315usxxd1) . on power - down, once vcc falls below the reset threshold, rst stays low and is guaranteed to be 0.4v or less until vcc drops below 1v. m anual reset the manual - reset input (mr) allows reset to be triggered by a pushbutton switch. the switch is effectively debounced by the 1.6ms (pt7m6315usxxd1) or 26ms ( pt7m 6315usxx d 2 ) or 2 00ms (pt7m 6315usxxd3 ) or 1570ms (pt7m 6315usxx d4) reset pulse width. t.c. reference timing delay vcc gnd rst vcc resistor divider mr
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||| 2015 - 0 9 - 000 2 pt01 97 - 4 0 9 / 1 5 / 1 5 3 pt7m6315us supervisory circuit maximum ratings storage temperature ............................................................ - 65 o c to +150 o c ambient temperature with power applied .......................... - 40 o c to +85 o c supply voltage to ground potential (vcc to gnd) .............. - 0.3v to +7.0v dc input voltage (all inputs except vcc and gnd)...... - 0.3v to v cc +0.3v dc output current (all outputs) .......................................................... 3 0m a power dissipation .............. ............................ 320mw (depend on package) dc electrical characteristics (t a = - 40~85oc, unless otherwise noted. typical values are at t a = +25oc) description sym. test conditions min typ max unit supply vol tage v cc - 1.0 - 5.5 v supply current i cc v cc = 5.5v. no load. - - 12 a v cc = 3.6v. no load. - - 10 a voltage threshold v th - +25 ? th - ) ? th - (v th - ) ? ? ? th - ) ? th - (v th - ) ? hys v th+ - v th - * - 5 0 - mv output driving output low v ol i oh = 8ma, v cc = 5v - - 0.4 v i oh = 4ma, v cc = 3v - - 0.3 i oh = - 50a, v cc = 1v - - 0.09 open - drain output leakage current i lkg - - - 500 na i nternal pull - up resistor r p mr 32 63 100 k ? ih mr v cc < 4v 0.7vcc - - v v cc > 4v 2.4 - - input low voltage v il mr v cc < 4v - - 0.3vcc v v cc > 4v - - 0.8 note: v th - is voltage threshold when v cc falls from high to low. v th+ is voltage threshold when v cc rises from low to high. note: stresses greater than those listed under m aximum ratings may cause permanen t damage to the device. this is a stress rating only and functional operation of the device at these or any other condi - tions above those indicated in the operational sec - tions of this specification is not implied. exposure to absolute maximum rating condi tions for extended periods may affect reliability.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||| 2015 - 0 9 - 000 2 pt01 97 - 4 0 9 / 1 5 / 1 5 4 pt7m6315us supervisory circuit ac electrical characteristics t iming diagram (v cc = 1.0v to 5.5v, t a = - 40~85oc, unless otherwise noted. typical values are at t a = +25oc) sym. description test conditions part no. min typ max unit t rs reset timeout period - 6315usxxd1 1 1. 6 2 .2 ms 6315usxx d 2 17 26 40 ms - 6315usxxd3 140 200 280 ms - 6315usxx d4 1120 1570 2240 ms t rpd delay - - - 17 - ? sen sensitivity - - 20 - - ? md mr to reset delay - - - 500 - ns t mr mr pulse width - - 1 - - ? vcc v rst 1v 0v t rs t sen t rs t rpd 1v 0v uncertain state mr t mr 0v t rs 0.8v rst t md v ih
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||| 2015 - 0 9 - 000 2 pt01 97 - 4 0 9 / 1 5 / 1 5 5 pt7m6315us supervisory circuit m echanical information sot 143 - 4 ordering information part number package code package pt7m6315usxx d 1 tbe x tb lead free and green sot143 - 4 , tape & reel pt7m6315usxx d 2 tbe x tb lead free and green sot143 - 4 , tape & reel pt7m6315usxx d 3 tbe x tb lead free and green sot143 - 4 , tape & reel pt7m6315usxx d 4 tbe x tb lead free and green sot143 - 4 , tape & reel note: ? xx refer to voltage range, see below table 1. ? e=lead - free and green packaging ? adding x suffix=tape/reel ? contact pericom for availability.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||| 2015 - 0 9 - 000 2 pt01 97 - 4 0 9 / 1 5 / 1 5 6 pt7m6315us supervisory circuit table 1. suffi x xx definition of pt7m 6315usxx sot - 143 package top marking instruction sample: t alj part no.: pt7m 6315us25d3 date code: year 2003 ww10 table 2 product marking c ode part no. code part no. code part no. code pt7m 6315us 25d3 ta pt7m 6315us 34d3 uk pt7m 6315us 43d3 vu pt7m 6315us 25d4 tb pt7m 6315us 34d4 ul pt7m 6315us 43d4 vv pt7m 6315us 26d3 te pt7m 6315us 35d3 uo pt7m 6315us 44d3 vy pt7m 6315us 26d4 tf pt7m 6315us 35d4 up pt7m 6315us 44d4 vz pt7m 6315us 27d3 ti pt7m 6315us 36d3 us pt7m 6315us 45d3 wc pt7m 6315us 27d4 tj pt7m 6315us 36d4 ut pt7m 6315us 45d4 wd pt7m 6315us 28d3 tm pt7m 6315us 37d3 uw pt7m 6315us 46d3 wg pt7m 6315us 28d4 t n pt7m 6315us 37d4 ux pt7m 6315us 46d4 wh pt7m 6315us 29d3 tq pt7m 6315us 38d3 va pt7m 6315us 47d3 wk pt7m 6315us 29d4 tr pt7m 6315us 38d4 vb pt7m 6315us 47d4 wl pt7m 6315us 30d3 tu pt7m 6315us 39d3 ve pt7m 6315us 48d3 wo pt7m 6315us 30d4 tv pt7m 6315us 39d4 vf pt7m 6315us 48d4 w p pt7m 6315us 31d3 ty pt7m 6315us 40d3 vi pt7m 6315us 49d3 ws pt7m 6315us 31d4 tz pt7m 6315us 40d4 vj pt7m 6315us 49d4 wt pt7m 6315us 32d3 uc pt7m 6315us 41d3 vm pt7m 6315us 50d3 ww pt7m 6315us 32d4 ud pt7m 6315us 41d4 vn pt7m 6315us 50d4 wx pt7m 6315us 33d3 ug pt7m 6315us 42d3 vq pt7m 6315us29 d 2 pm pt7m 6315us 33d4 uh pt7m 6315us 42d4 vr pt7m 6315us30 d 2 pn pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom technology incorporation reserves the right to make changes t o its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom technology does not assume any responsibility for use of any cir cuitry described other than the circuit ry embodied in pericom technology product. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom technology incorporation. suffix xx v th - (v) suffix xx v th - (v) suffix xx v th - (v) suffix xx v th - (v) 18 1.8 27 2.7 36 3.6 45 4.5 19 1.9 28 2.8 37 3.7 46 4.6 20 2.0 29 2.9 38 3.8 47 4.7 21 2.1 30 3.0 39 3.9 48 4.8 22 2.2 31 3.1 40 4.0 49 4.9 23 2.3 32 3.2 41 4.1 50 5.0 24 2.4 33 3.3 42 4.2 25 2.5 34 3.4 43 4.3 26 2.6 35 3.5 44 4.4 t a lj part no. 2 bit code (see table 2 ) date code year & work week
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